PMOS Regulated Cascode SI Memory Cell using Clock Feedthrough Cancellation

This paper presents a high performance switched current memory cell The cell is designed for reduced supply voltages and low power For audio applications an accuracy around bits is mandatory The accuracy of the basic memory cell su ers from channel modulation and clock feedthrough errors The channel length modulation error is reduced by cascoding the memory transistor The high gain of the cascode implies that the memory transistor may be operated in its linear mode to improve accuracy The implementation of a single regulated cascode is compared to a double regulated cascode A new clock feedthrough cancellation technique reduces errors due to charge injection of mos switches hspice simulations show that the single cascoded memory cell is accurate up to ppm or bit at a ns conversion time for input currents between A and A For a current range A Iin A the double cascoded memory cell attains a bits accuracy at a ns conversion time Both circuits dissipate an average W for an A input current from a V power supply The accuracy is achieved over a wide range of input currents which makes the memory cell of interest as a building block for si ad or da converters However measurements must show the actual performances of the design